1. Field of the Invention
This invention generally relates to oversampling analog-to-digital converters of sigma-delta type and, more particularly, to oversampling analog-to-digital converters of sigma-delta type which use chopper-stabilized amplifiers in their Miller integrators.
2. General Description of the Prior Art High resolution analog-to-digital (or A/D) signal conversion can be achieved with lower resolution components through the use of oversampled interpolative (or sigma-delta) modulation followed by digital low pass filtering and decimation. Oversampling refers to operation of the modulator at a rate many times above the signal Nyquist rate, whereas decimation refers to reduction of the clock rate down to the Nyquist rate.
Sigma delta modulators (sometimes referred to as delta sigma modulators) have been used in analog-to-digital converters for some time. Detailed general information can be obtained from the following technical articles which are hereby incorporated by reference.
1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", J. C. Candy, IEEE Transactions on Communications, Vol. COM-22, No. 3, pp. 298-305, March 1974 PA1 2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", J. C. Candy, et al., IEEE Transactions on Communications, Vol. COM-24, No. 11, pp. 1268-1275, November 1976 PA1 3) "A Use of Double Integration in Sigma Delta Modulation", J. C. Candy, IEEE Transactions on Communications, Vol. COM-33, No. 3, pp. 249-258, March 1985.
Substantial effort has been expended in the field of oversampled analog-to-digital converter design to develop plural-order sigma-delta modulators in order to obtain higher resolution for a given oversampling ratio. As the term "order" is used herein, the order of a sigma-delta modulator is determined directly by how many times the error between its output and input signals is integrated with respect to time, while the order of a sigma-delta converter stage within a plural-stage sigma-delta A/D converter is determined directly by how many times the input signal to that stage is integrated with respect to time in reaching the output connection of that stage.
In the above type of analog-to-digital converter, resolution is predominantly governed by two factors: (1) the ratio of the modulator clock to the Nyquist rate, henceforth referred to as the oversampling ratio, and (2) the "order" of the modulator. "Order" in this context is analogous to the order of a frequency selective filter and indicates the relative degree of spectral shaping that is provided by the modulator. As with a filter, higher selectivity is obtainable with a higher order at the expense of increased hardware complexity. In recognition of these two factors, recent implementations of high resolution oversampled analog-to-digital converters have employed both large oversampling ratios and high modulator order. However, practical considerations can limit the extent to which oversampling rate and modulator order can be taken. For instance, for a given modulator clock rate, the oversampling ratio is inversely proportional to the Nyquist rate after decimation and thus cannot be made arbitrarily high without sacrificing conversion rate. Different considerations set bounds on the modulator order. Implementations of order greater than two, using a single quantizer, can be shown to be only conditionally stable and are therefore not viable.
An alternative approach can be used to effectively provide high order noise shaping with cascaded low-order modulators to ensure stable operation. An improved third-order sigma-delta analog-to-digital converter which achieves third-order noise-shaping with reduced sensitivity to component mismatching, finite amplifier gain and other nonideal circuit attributes, herein referred to as "nonidealities" was sought by the present inventor. Improved architectures for third-order sigma-delta analog-to-digital converters which can be implemented as sampled data switched-capacitor circuits were sought. It was also sought to provide third-order quantization noise-shaping in a third-order sigma-delta analog-to-digital converter with a modulator network architecture that employs amplifiers of finite gain and is relatively insensitive to normal circuit nonidealities so that A/D converter resolution approaching the theoretical limits can be obtained. A new third-order sigma-delta analog-to-digital converter network was developed by the inventor that exhibits significantly reduced sensitivity to the practical nonidealities that normally limit resolution of prior-art third-order sigma-delta analog-to-digital converter networks, i.e., component mismatching, amplifier non-linearity, finite gain, excessive settling time, and limited signal dynamic range. Thorough simulations, taking into account nonidealities, indicate that 16-bit resolution at an 80 kHz conversion rate is achievable with the new A/D converter network operated at an oversampling ratio of 64. This performance is attainable despite component matching of only 2% and op amp gains as low as 1000. The realization of these performance levels despite only modest required circuit specifications indicate that a low cost, highly manufacturable A/D converter network is now practicable. MOS, CMOS, BiCMOS, GaAs. or Bipolar integrated circuit technologies can be used with this new A/D converter network to implement a completely monolithic A/D converter network with no external components other than decoupling capacitors. The modest complexity of the new A/D converter network provides for efficient implementation of digital signal processing chips with high resolution multi-channel analog interfaces.
The inventor finds that the practical realization of this new A/D converter network, as well as the practical realization of other A/D converter networks of sigma-delta type that are being developed, is much enhanced by employing chopper stabilization of the operational amplifier used in the initial integrator for error signal. F. Yassa, S. Garverick, G. Ngo, R. Hartley, J. Prince, J. Lam, S. Noujaim, R. Korsunsky and J. Thomas in their paper entitled "A Multi-Channel Digital Demodulator for LVDT and RVDT Position Sensors" appearing on pages 20.5.1-20.5.5 of the IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE DIGEST 0F TECHNICAL PAPERS, CH2671-6/89/0000-0125-$1.00 c. 1989 IEEE describe the use of chopper stabilization in a sigma-delta (or delta-sigma) modulator to eliminate amplifier offset and component mismatch and to generate a dither signal which is added to the input to achieve higher sensitivity to low-amplitude signals. The zero of the decimation filter Yassa et al. used after the sigma-delta modulator is matched to the frequency of the chopping signal, better to suppress the dither signal and other modulator artifacts produced at the chopping frequency. The chopper stabilization moves the flicker (or 1/f) noise of the amplifier in the frequency spectrum from baseband to sidebands of the chopping frequency, the lower of which sidebands aliases into baseband to a degree. As long as high resolution is not demanded from the oversampling A/D converter network, the 1/f noise aliased into the baseband is less than the difference between adjacent quantizing levels even if the frequency of the chopping signal in cycles per second is the same as the rate of the output from the decimation filter in samples per second.
As one strives for increased resolution in the digitized output, however, the 1/f noise aliased into the baseband becomes more than the difference between adjacent quantizing levels if the frequency of the chopping signal in cycles per second is the same as the rate of the output from the decimation filter in samples per second. The inventor finds that this problem is ameliorated if the chopping rate is increased to be a multiple, more than one, times the output rate from the decimation filter. Faster chopping rates introduce a tendency towards increased non-linearity arising from the settling of the chopper-stabilized amplifier after each switching thereof, the inventor finds. So, it is usually preferable not to increase the chopping rate to equal one half the oversampling rate. Rather, the inventor finds, it is usually preferable in an oversampling A/D converter network, from the standpoint of achieving the highest resolution in terms of bits, to choose the chopping rate to be a lower multiple of the rate of the output from the decimation filter. This lower multiple is preferably chosen as close as possible to where the characteristics associated with 1/f noise and with the non-linearity arising from the settling of the chopper-stabilized amplifier after each switching thereof, respectively, exhibit their cross-over in values. Then, the difference between adjacent quantizing levels can be minimized to make available the most number of bits of resolution.